library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

use std.textio.all;

use work.Kamera;
use work.SimUtils.all;
use work.StringPack.all;

entity testbench is
end testbench;

architecture a of testbench is
	signal clk : bit;
	signal serIn : bit := '1';
	signal serOut : bit;
	signal led : bit;

	signal spiclk : bit;	
	signal spidat : std_ulogic;
	signal pwdn : bit;
	
	signal clkEnable : boolean := true;
	
	signal data_recv : byte;
	
begin

	KameraInst : entity Kamera(Behavioral) port map (
		clk => clk,
		rs232RX => serIn,
		rs232TX => serOut,
		SCL => spiclk,
		SDA => spidat,
		PWDN => pwdn,
		PCLK => '0',
		HREF => '0',
		VSYNC => '0',
		D => "0000000000"
	);
	
	--spidat <= '1';
	
	ClockSrc : ClockSource
		generic map ( freq => 50 MHz )
		port map ( clk => clk, enable => clkEnable );

	-- run tests
	process
		variable d : byte;
	begin
		wait for 10 us;
		report "Perform Sccb Read";
		sendRs232(19.2 kBaud, x"02", serIn);
		sendRs232(19.2 kBaud, x"42", serIn);
		sendRs232(19.2 kBaud, x"F2", serIn);
		report "Read result";
		recvRs232(19.2 kBaud, d, serOut);
		report "Recv: " & str(d);
		data_recv <= d;
		wait for 1 ms;
		clkEnable <= false;
		wait;
	end process;
	
	-- simulate slave
	process
	begin
		wait;
	end process;

end a;