library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity Seg7Display is
	Port (Clk : in std_logic;
			Seg7 : out std_logic_vector(7 downto 0);
			Seg7DE : out std_logic_vector(3 downto 0);
			Data : in std_logic_vector(15 downto 0));
end Seg7Display;

architecture Behavioral of Seg7Display is
	signal Clock : std_logic;
	signal Clocks : std_logic_vector(16 downto 0);
	signal SegDataIn : std_logic_vector(3 downto 0);
	signal SegDataOut : std_logic_vector(6 downto 0);
begin

	process(Clk)
		begin
			if Clk'event and Clk='1' then
				Clocks <= Clocks + '1';
			end if;
	end process;

	Clock <= Clocks(16);

	with SegDataIn select
		SegDataOut <=	"0111111" when "0000",
							"0000110" when "0001",
							"1011011" when "0010",
							"1001111" when "0011",
							"1100110" when "0100",
							"1101101" when "0101",
							"1111101" when "0110",
							"0000111" when "0111",
							"1111111" when "1000",
							"1101111" when "1001",
							"1110111" when "1010",
							"1111100" when "1011",
							"0111001" when "1100",
							"1011110" when "1101",
							"1111001" when "1110",
							"1110001" when others;
	Seg7 <= not ("0" & SegDataOut);
	
	process(Clock)
		variable State: integer range 0 to 3:=0;
	begin
		if Clock'event and Clock='1' then
			case State is
				when 0 => 
					SegDataIn <= Data(3 downto 0);
					Seg7DE <= not "0001";
					State := State + 1;
				when 1 => 
					SegDataIn <= Data(7 downto 4);
					Seg7DE <= not "0010";
					State := State + 1;
				when 2 =>
					SegDataIn <= Data(11 downto 8);
					Seg7DE <= not "0100";
					State := State + 1;
				when others =>
					SegDataIn <= Data(15 downto 12);
					Seg7DE <= not "1000";
					State := 0;
			end case;
		end if;
	end process;

end Behavioral;