library IEEE;
use IEEE.STD_LOGIC_1164.all;

package MemPack is

	subtype tData3B is std_logic_vector(23 downto 0);
	subtype tData4B is std_logic_vector(31 downto 0);
	type tArray is array(0 to 2) of tData4B;

	type tState is record
		dat : tArray;
		pos : integer range 0 to 3; -- cursor pos in 3 Byte view
	end record;
	
	constant tState_Init : tState := (
		dat => (x"00000000",x"00000000",x"00000000"),
		pos => 0
	);

	-- Memory write (pack 3 to 4)

	procedure Mem3to4_writeSetInpData (
		variable state : inout tState; 
		variable data : in tData3B
	);
	
	function Mem3to4_writeCommitRequired ( state : in tState ) return boolean;
	function Mem3to4_writeGetOutpData ( state : in tState ) return tData4B;

	-- Memory read (unpack 4 to 3)

	procedure Mem3to4_readGetOutpData ( state : inout tState; dat : out tData3B );
	function Mem3to4_readFetchRequired ( state : in tState ) return boolean;
	
	procedure Mem3to4_readSetInpData ( 
		state : inout tState; 
		signal dat : in tData4B 
	);

end MemPack;

package body MemPack is

	-- Memory write (pack 3 to 4)

	procedure Mem3to4_writeSetInpData (
		variable state : inout tState; 
		variable data : in tData3B
	) is
	begin
		case state.pos is
			when 0 => 
				state.dat(0)(23 downto 0) := data;
				state.pos := 1;
			when 1 =>
				state.dat(0)(31 downto 24) := data(7 downto 0);
				state.dat(1)(15 downto 0) := data(23 downto 8);
				state.pos := 2;
			when 2 =>
				state.dat(1)(31 downto 16) := data(15 downto 0);
				state.dat(2)(7 downto 0) := data(23 downto 16);
				state.pos := 3;
			when 3 =>
				state.dat(2)(31 downto 8) := data;
				state.pos := 0;
			when others => null;
		end case;
	end Mem3to4_writeSetInpData;

	function Mem3to4_writeCommitRequired ( state : in tState ) return boolean is
	begin
		case state.pos is -- pos is next write position here! (we use variables)
			when 0 => return True;
			when 1 => return False;
			when 2 => return True;
			when 3 => return True;
			when others => return False;
		end case;
	end Mem3to4_writeCommitRequired;
	
	
	function Mem3to4_writeGetOutpData ( state : in tState ) return tData4B is
	begin
		case state.pos is -- pos is next write position here! (we use variables)
			when 1 => return x"ffffffff"; -- invalid case
			when 2 => return state.dat(0);
			when 3 => return state.dat(1);
			when 0 => return state.dat(2);
			when others => return x"00000000";
		end case;
	end Mem3to4_writeGetOutpData;

	-- Memory read (unpack 4 to 3)

	procedure Mem3to4_readGetOutpData ( state : inout tState; dat : out tData3B ) is
	begin
		case state.pos is
			when 0 => 
				dat := state.dat(0)(23 downto 0);
				state.pos := 1;
			when 1 =>
				dat(7 downto 0) := state.dat(0)(31 downto 24);
				dat(23 downto 8) := state.dat(1)(15 downto 0);
				state.pos := 2;
			when 2 =>
				dat(15 downto 0) := state.dat(1)(31 downto 16);
				dat(23 downto 16) := state.dat(2)(7 downto 0);
				state.pos := 3;
			when 3 =>
				dat := state.dat(2)(31 downto 8);
				state.pos := 0;
			when others => null;
		end case;
	end Mem3to4_readGetOutpData;
	
	function Mem3to4_readFetchRequired ( state : in tState ) return boolean is
	begin
		case state.pos is -- pos is next read position here! (we use variables)
			when 0 => return True;
			when 1 => return True;
			when 2 => return True;
			when 3 => return False;
			when others => return False;
		end case;
	end Mem3to4_readFetchRequired;
	
	procedure Mem3to4_readSetInpData ( 
		state : inout tState; 
		signal dat : in tData4B 
	) is
	begin
		case state.pos is -- pos is next read position here! (we use variables)
			when 0 =>
				state.dat(0) := dat;
			when 1 =>
				state.dat(1) := dat;
			when 2 =>
				state.dat(2) := dat;
			when 3 =>
				null; -- invalid case
			when others => null;
		end case;
	end Mem3to4_readSetInpData;



end MemPack;