----------------------------------------------------------------------------
--  Projekt "Burst-Master mit 4 KByte RAM"
--  (Target-Interface zur Steuerung)
--  Erlaeuterung in der HTML-Dokumentation.
----------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity target_control is
  port ( 
    -- Signale des PCI-Interfaces 
    RST                  : in std_logic;
    CLK                  : in std_logic;
    BASE_HIT             : in std_logic_vector(7 downto 0);
    S_DATA               : in std_logic;
    S_WRDN               : in std_logic;
    ADDR                 : in std_logic_vector(31 downto 0);
    S_DATA_VLD           : in std_logic;
    S_READY              : out std_logic;
    S_TERM               : out std_logic;
    S_ABORT              : out std_logic;

    -- im Modul gebildete Ausgangssignale
    OE_PCI_START_REG     : out std_logic;
    OE_XFER_COUNT_REG    : out std_logic;
    OE_STATUS_REG        : out std_logic;
    OE_INTR_FLAG         : out std_logic;
    LOAD_PCI_START_REG   : out std_logic;
    LOAD_XFER_COUNT_REG  : out std_logic;
    LOAD_COMMAND_REG     : out std_logic
  );
end target_control;

architecture rtl of target_control is

signal bar_0_rd, bar_0_wr      : std_logic;

signal pci_start_reg_selected  : std_logic;
signal xfer_count_reg_selected   : std_logic;
signal control_reg_selected    : std_logic;
signal intr_flag_selected    : std_logic;
       
begin

  decode_hit : process (CLK, RST)
  begin
    if RST = '1' then
      bar_0_rd <= '0';
      bar_0_wr <= '0';
    elsif CLK'event and CLK = '1' then
      if BASE_HIT(0) = '1' then            
        bar_0_rd <= not S_WRDN;
        bar_0_wr <= S_WRDN;
      elsif S_DATA = '0' then
        bar_0_rd <= '0';
        bar_0_wr <= '0';
      end if;
    end if;
  end process;

  pci_start_reg_selected  <= '1' when ADDR(11 downto 2) = x"00" & "00" else '0';
  xfer_count_reg_selected <= '1' when ADDR(11 downto 2) = x"00" & "01" else '0';
  control_reg_selected    <= '1' when ADDR(11 downto 2) = x"00" & "10" else '0';
  intr_flag_selected      <= '1' when ADDR(11 downto 2) = x"00" & "11" else '0';
                       

  LOAD_PCI_START_REG  <= bar_0_wr and S_DATA_VLD and pci_start_reg_selected;
  LOAD_XFER_COUNT_REG <= bar_0_wr and S_DATA_VLD and xfer_count_reg_selected;
  LOAD_COMMAND_REG    <= bar_0_wr and S_DATA_VLD and control_reg_selected;
 
  OE_PCI_START_REG  <= bar_0_rd and S_DATA and pci_start_reg_selected;
  OE_XFER_COUNT_REG <= bar_0_rd and S_DATA and xfer_count_reg_selected;
  OE_STATUS_REG     <= bar_0_rd and S_DATA and control_reg_selected;
  OE_INTR_FLAG      <= bar_0_rd and S_DATA and intr_flag_selected;


  -- Target immer bereit, Single Transfers, keine Target Aborts
  term_control: process (RST, CLK)
  begin
    if RST = '1' then

      -- hier die invertierten Default-Werte
      S_READY <= '0'; 
      S_TERM  <= '0';
      S_ABORT <= '1';

    elsif CLK'event and CLK = '1' then

     -- hier die richtigen Werte
      S_READY <= '1';
      S_TERM  <= '1';
      S_ABORT <= '0';

    end if;
  end process;

end rtl;