----------------------------------------------------------------------------
--  Projekt "Burst-Master mit 4 KByte RAM"
--
--  8 RAMB4_S4 Komponenten der Xilinx Bibiothek bilden ein 
--  1 K x 32 Bit = 4 KByte grosses RAM mit bidirektionalem Tristate-Datenbus
----------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


-- Einbinden der Xilinx Bibliothek
library UNISIM;
use UNISIM.Vcomponents.ALL;


entity RAMB4_S32 is
   port ( 
     ADDR : in std_logic_vector(9 downto 0);
     CLK  : in std_logic;
     DI   : in std_logic_vector(31 downto 0);
     EN   : in std_logic;
     RST  : in std_logic;
     WE   : in std_logic ;
     DO   : out std_logic_vector(31 downto 0)
   );
end RAMB4_S32;

architecture rtl of RAMB4_S32 is

begin
  
  -- Block RAM fuer die Datenbits 0 - 3
  blockram_inst0 : RAMB4_S4
    port map (
      ADDR => ADDR,
      CLK  => CLK, 
      DI   => DI(3 downto 0),
      EN   => EN,
      RST  => RST,
      WE   => WE,
      DO   => DO(3 downto 0)
    );

  -- Block RAM fuer die Datenbits 4 - 7
  blockram_inst1 : RAMB4_S4
    port map (
      ADDR => ADDR,
      CLK  => CLK, 
      DI   => DI(7 downto 4),
      EN   => EN,
      RST  => RST,
      WE   => WE,
      DO   => DO(7 downto 4)
    );

  -- Block RAM fuer die Datenbits 8 - 11
  blockram_inst2 : RAMB4_S4
    port map (
      ADDR => ADDR,
      CLK  => CLK, 
      DI   => DI(11 downto 8),
      EN   => EN,
      RST  => RST,
      WE   => WE,
      DO   => DO(11 downto 8)
    );

  -- Block RAM fuer die Datenbits 12 - 15
  blockram_inst3 : RAMB4_S4
    port map (
      ADDR => ADDR,
      CLK  => CLK, 
      DI   => DI(15 downto 12),
      EN   => EN,
      RST  => RST,
      WE   => WE,
      DO   => DO(15 downto 12)
    );

  -- Block RAM fuer die Datenbits 16 - 19
  blockram_inst4 : RAMB4_S4
    port map (
      ADDR => ADDR,
      CLK  => CLK, 
      DI   => DI(19 downto 16),
      EN   => EN,
      RST  => RST,
      WE   => WE,
      DO   => DO(19 downto 16)
    );

  -- Block RAM fuer die Datenbits 20 - 23
  blockram_inst5 : RAMB4_S4
    port map (
      ADDR => ADDR,
      CLK  => CLK, 
      DI   => DI(23 downto 20),
      EN   => EN,
      RST  => RST,
      WE   => WE,
      DO   => DO(23 downto 20)
    );

  -- Block RAM fuer die Datenbits 24 - 27
  blockram_inst6 : RAMB4_S4
    port map (
      ADDR => ADDR,
      CLK  => CLK, 
      DI   => DI(27 downto 24),
      EN   => EN,
      RST  => RST,
      WE   => WE,
      DO   => DO(27 downto 24)
    );

  -- Block RAM fuer die Datenbits 28 - 31
  blockram_inst7 : RAMB4_S4
    port map (
      ADDR => ADDR,
      CLK  => CLK, 
      DI   => DI(31 downto 28),
      EN   => EN,
      RST  => RST,
      WE   => WE,
      DO   => DO(31 downto 28)
    );

end rtl;