----------------------------------------------------------------------------
--  Projekt "Burst-Master mit 4 KByte RAM"
--  Behandlung unbenutzter LogiCore PCI Interface Eingaenge
----------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity benign is
  port ( 
    SUB_DATA    : out std_logic_vector(31 downto 0);
    KEEPOUT     : out std_logic;
    C_READY     : out std_logic;
    C_TERM      : out std_logic;
    REQUESTHOLD : out std_logic;
    CFG_SELF    : out std_logic
  );
end benign;

architecture rtl of benign is

begin
  -- Card Bus CIS Pointer Daten / Subsystem ID Daten
  SUB_DATA    <= x"FFFFFFFF" ;
    
  -- ADIO-Bus immer mit LogiCore PCI Interface verbunden
  KEEPOUT     <= '0'; -- ADIO-Bus immer enabled

  -- Steuersignale für Konfigurationstransaktionen
  C_READY     <= '1';  
  C_TERM      <= '1';

  -- Initiator Stuersignale
  REQUESTHOLD <= '0';
  CFG_SELF    <= '0';
 
end rtl;