---------------------------------------------------------------------------- -- -- File: userapp.vhd -- Rev: 3.0.0 -- -- This is an example template for the user backend application. -- -- Copyright (c) 2002 Xilinx, Inc. All rights reserved. -- ---------------------------------------------------------------------------- -- Projekt "Interrupt" -- Eine ausfuehrliche Beschreibung befindet sich in der HTML-Dokumentation. ---------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.STD_LOGIC_ARITH.ALL; entity userapp is port (-- Interface to PCI Logicore. FRAMEQ_N : in std_logic; TRDYQ_N : in std_logic; IRDYQ_N : in std_logic; STOPQ_N : in std_logic; DEVSELQ_N : in std_logic; ADDR : in std_logic_vector( 31 downto 0); ADIO : inout std_logic_vector( 31 downto 0); CFG_VLD : in std_logic; CFG_HIT : in std_logic; C_TERM : out std_logic; C_READY : out std_logic; ADDR_VLD : in std_logic; BASE_HIT : in std_logic_vector( 7 downto 0); S_TERM : out std_logic; S_READY : out std_logic; S_ABORT : out std_logic; S_WRDN : in std_logic; S_SRC_EN : in std_logic; S_DATA_VLD : in std_logic; S_CBE : in std_logic_vector( 3 downto 0); PCI_CMD : in std_logic_vector( 15 downto 0); REQUEST : out std_logic; REQUESTHOLD : out std_logic; COMPLETE : out std_logic; M_WRDN : out std_logic; M_READY : out std_logic; M_SRC_EN : in std_logic; M_DATA_VLD : in std_logic; M_CBE : out std_logic_vector( 3 downto 0); TIME_OUT : in std_logic; CFG_SELF : out std_logic; M_DATA : in std_logic; DR_BUS : in std_logic; I_IDLE : in std_logic; M_ADDR_N : in std_logic; IDLE : in std_logic; B_BUSY : in std_logic; S_DATA : in std_logic; BACKOFF : in std_logic; INTR_N : out std_logic; PERRQ_N : in std_logic; SERRQ_N : in std_logic; KEEPOUT : out std_logic; CSR : in std_logic_vector( 39 downto 0); SUB_DATA : out std_logic_vector( 31 downto 0); CFG : in std_logic_vector(255 downto 0); RST : in std_logic; CLK : in std_logic; USER_LED : out std_logic; USER_BUTTON : in std_logic ); end userapp; architecture rtl of userapp is attribute syn_edif_bit_format : string; attribute syn_edif_scalar_format : string; attribute syn_noclockbuf : boolean; attribute syn_hier : string; attribute syn_edif_bit_format of rtl : architecture is "%u<%i>"; attribute syn_edif_scalar_format of rtl : architecture is "%u"; attribute syn_noclockbuf of rtl : architecture is true; attribute syn_hier of rtl : architecture is "hard"; -- Steuersignale signal bar_0_rd : std_logic; signal intr_reg_select : std_logic; signal oe_intr_reg, oe_dummy : std_logic; signal oe_intr_reg_fell : std_logic; -- Register signal intr_reg : std_logic; begin -- Ausgabe des Interrupt-Flags USER_LED <= intr_reg; -- Zuweisung des Interrupt-Flags an die Interrupt-Leitung des PCI Interfaces INTR_N <= intr_reg; -- Lesezugriff auf das PCI-Target (Interrupt-Flag) erkennen decode_hit : process (CLK, RST) begin if RST = '1' then bar_0_rd <= '0'; elsif CLK'event and CLK = '1' then if BASE_HIT(0) = '1' then bar_0_rd <= not S_WRDN; elsif S_DATA = '0' then bar_0_rd <= '0'; end if; end if; end process; -- Interrupt-Flag wird adressiert intr_reg_select <= '1' when ADDR(11 downto 2) = x"00" & "00" else '0'; -- Output Enables und Ausgabe auf den ADIO-Bus oe_intr_reg <= bar_0_rd and S_DATA and intr_reg_select; oe_dummy <= bar_0_rd and S_DATA and not intr_reg_select; ADIO <= x"0000000" & "000" & intr_reg when oe_intr_reg = '1' else x"00000000" when oe_dummy = '1' else (others => 'Z'); -- oe_intr_reg_fell fuer einen Takt setzen, wenn eine fallende Flanke beim -- Signal oe_intr_reg beobachtet wird. -- (Ende des Lesezugriffs auf das Interrupt-Flag.) process (CLK, RST) variable oe_intr_reg_delay : std_logic; begin if RST = '1' then oe_intr_reg_delay := '0'; elsif CLK'event and CLK = '1' then if oe_intr_reg = '0' and oe_intr_reg_delay = '1' then oe_intr_reg_fell <= '1'; else oe_intr_reg_fell <= '0'; end if; oe_intr_reg_delay := oe_intr_reg; end if; end process; -- Interrupt-Flag (negiert!) -- o Setzen (=0), wenn User-Button gedrueckt. -- o Loeschen (=1) nach einem Lesezugriff process (CLK, RST) begin if RST = '1' then intr_reg <= '1'; elsif CLK'event and CLK = '1' then if oe_intr_reg_fell = '1' then intr_reg <= '1'; elsif USER_BUTTON = '0' then intr_reg <= '0'; end if; end if; end process; -- Target: Single Transfers, immer bereit. term_control: process (RST, CLK) begin if RST = '1' then -- hier die invertierten Default-Werte S_READY <= '0'; S_TERM <= '0'; elsif CLK'event and CLK = '1' then -- hier die richtigen Werte S_READY <= '1'; s_TERM <= '1'; end if; end process; -- Card Bus CIS Pointer Daten / Subsystem ID Daten SUB_DATA <= x"FFFFFFFF" ; -- ADIO-Bus immer mit LogiCore PCI Interface verbunden KEEPOUT <= '0'; -- ADIO-Bus immer enabled -- Steuersignale für Konfigurationstransaktionen C_READY <= '1'; C_TERM <= '1'; -- Initiator Stuersignale REQUEST <= '0'; REQUESTHOLD <= '0'; CFG_SELF <= '0'; static_config: process (CLK, RST) begin if RST = '1' then -- hier die invertierten Default-Werte, Kommentare siehe unten S_ABORT <= '1'; COMPLETE <= '0'; M_WRDN <= '1'; M_READY <= '0'; M_CBE <= "1001"; elsif (CLK'event and CLK='1') then -- Signalisierung von schweren Fehlern nicht vorgesehen S_ABORT <= '0'; -- ordnungsgemaesses Abschalten der Initiator-Funktionen COMPLETE <= '1'; M_WRDN <= '0'; M_READY <= '1'; M_CBE <= "0110"; end if; end process; end rtl;