--------------------------------------------------------------------------
--  File:   cfg.vhd
--  Rev:    v3.103
--
--  This is the user configurable options file for Xilinx's PCI Logicore.
--  Normally generated by the web-based PCI CORE Customization tool.
--
--  Copyright (c) 1999 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------
--  Projekt "Interrupt"
--  Eine ausfuehrliche Beschreibung befindet sich in der HTML-Dokumentation.
----------------------------------------------------------------------------


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;


entity cfg is
    port(
          CFG        : out   std_logic_vector(255 downto 0)
         );
end cfg;


architecture rtl of cfg is

  -- declare some signals for outputs.
  signal   cfg_int : bit_vector(255 downto 0) ;


  -- declare literals for use later
  constant MEMORY       : bit := '0' ;
  constant IO           : bit := '1' ;


  constant DISABLE      : bit := '0' ;
  constant ENABLE       : bit := '1' ;

  constant PREFETCH     : bit := '1' ;
  constant NOFETCH      : bit := '0' ;
  constant IO_PREFETCH  : bit := '1' ;

  constant TYPE00       : bit_vector(1 downto 0) := "00" ;
  constant TYPE01       : bit_vector(1 downto 0) := "01" ;
  constant TYPE10       : bit_vector(1 downto 0) := "10" ;
  constant IO_TYPE      : bit_vector(1 downto 0) := "11" ;

  constant SIZE2G   : bit_vector(31 downto 0) := X"80000000";
  constant SIZE1G   : bit_vector(31 downto 0) := X"c0000000";
  constant SIZE512M : bit_vector(31 downto 0) := X"e0000000";
  constant SIZE256M : bit_vector(31 downto 0) := X"f0000000";
  constant SIZE128M : bit_vector(31 downto 0) := X"f8000000";
  constant SIZE64M  : bit_vector(31 downto 0) := X"fc000000";
  constant SIZE32M  : bit_vector(31 downto 0) := X"fe000000";
  constant SIZE16M  : bit_vector(31 downto 0) := X"ff000000";
  constant SIZE8M   : bit_vector(31 downto 0) := X"ff800000";
  constant SIZE4M   : bit_vector(31 downto 0) := X"ffc00000";
  constant SIZE2M   : bit_vector(31 downto 0) := X"ffe00000";
  constant SIZE1M   : bit_vector(31 downto 0) := X"fff00000";
  constant SIZE512K : bit_vector(31 downto 0) := X"fff80000";
  constant SIZE256K : bit_vector(31 downto 0) := X"fffc0000";
  constant SIZE128K : bit_vector(31 downto 0) := X"fffe0000";
  constant SIZE64K  : bit_vector(31 downto 0) := X"ffff0000";
  constant SIZE32K  : bit_vector(31 downto 0) := X"ffff8000";
  constant SIZE16K  : bit_vector(31 downto 0) := X"ffffc000";
  constant SIZE8K   : bit_vector(31 downto 0) := X"ffffe000";
  constant SIZE4K   : bit_vector(31 downto 0) := X"fffff000";
  constant SIZE2K   : bit_vector(31 downto 0) := X"fffff800";
  constant SIZE1K   : bit_vector(31 downto 0) := X"fffffc00";
  constant SIZE512  : bit_vector(31 downto 0) := X"fffffe00";
  constant SIZE256  : bit_vector(31 downto 0) := X"ffffff00";
  constant SIZE128  : bit_vector(31 downto 0) := X"ffffff80";
  constant SIZE64   : bit_vector(31 downto 0) := X"ffffffc0";
  constant SIZE32   : bit_vector(31 downto 0) := X"ffffffe0";
  constant SIZE16   : bit_vector(31 downto 0) := X"fffffff0";

  begin

--------------------------------------------------------------
-- Configure Device, Vendor ID, Class Code, and Revision ID
--------------------------------------------------------------

  -- Device ID and Vendor ID
  cfg_int(151 downto 120) <= X"030010ee";

  -- Class Code and Revision ID
  cfg_int(183 downto 152) <= X"0b400000";

--------------------------------------------------------------
-- Configure Subsystem ID and SubVendor ID
--------------------------------------------------------------

  -- Subsystem ID and SubVendor ID
  cfg_int(215 downto 184) <= X"00000000" ;

  -- External Subsystem ID and Subvendor ID
  cfg_int(114) <= DISABLE ;

--------------------------------------------------------------
-- Configure Base Address Registers
--------------------------------------------------------------

  -- BAR0
  cfg_int(0)              <= ENABLE ;
  cfg_int(32 downto 1)    <= SIZE4K ;
  cfg_int(33)             <= NOFETCH ;
  cfg_int(35 downto 34)   <= TYPE00 ;
  cfg_int(36)             <= MEMORY ;

  -- BAR1
  cfg_int(37)             <= DISABLE ;
  cfg_int(69 downto 38)   <= SIZE2G ;
  cfg_int(70)             <= NOFETCH ;
  cfg_int(72 downto 71)   <= TYPE00 ;
  cfg_int(73)             <= MEMORY ;

  -- BAR2
  cfg_int(74)             <= DISABLE ;
  cfg_int(106 downto 75)  <= SIZE2G ;
  cfg_int(107)            <= NOFETCH ;
  cfg_int(109 downto 108) <= TYPE00 ;
  cfg_int(110)            <= MEMORY ;

--------------------------------------------------------------
-- Configure MAX_LAT MIN_GNT
--------------------------------------------------------------

  -- MAX_LAT and MIN_GNT
  cfg_int(231 downto 224) <= X"00" ; 
  cfg_int(223 downto 216) <= X"00" ; 

-------------------------------------------------------------
--  Configure other PCI Header options
-------------------------------------------------------------

  -- Latency Timer Enable
  cfg_int(112) <= DISABLE ;

  -- Interrupt Enable
  cfg_int(113) <= ENABLE ;

-------------------------------------------------------------
--  For advanced users only.
-------------------------------------------------------------

  -- Capability List Enable
  cfg_int(116) <= DISABLE ;

  -- Capability List Pointer
  cfg_int(239 downto 232) <= X"00" ;

  -- User Config Space Enable
  cfg_int(118) <= DISABLE ;

  -- Interrupt Acknowledge
  cfg_int(240) <= DISABLE ;

-------------------------------------------------------------
--  Do not modify any of the following settings!
-------------------------------------------------------------

  -- Obsolete
  cfg_int(111) <= DISABLE ;

  -- Obsolete
  cfg_int(117) <= DISABLE ;

  -- Obsolete
  cfg_int(119) <= DISABLE ;

  -- Enable 66 MHz
  cfg_int(244) <= DISABLE ;

  -- Reserved
  cfg_int(254 downto 245) <= "0010000000";

  -- Do Not Modify
  cfg_int(115) <= DISABLE ;
  cfg_int(241) <= DISABLE ;
  cfg_int(242) <= DISABLE ;
  cfg_int(243) <= DISABLE ;
  cfg_int(255) <= DISABLE ;

  CFG <= to_stdlogicvector(cfg_int);

end rtl;