library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity rs232_out is
	Port (
			CLK: 	  in  std_logic;
			input: in std_logic_vector(8 downto 1);
			empty_flag: in std_logic := '0';
			next_flag: out std_logic := '0';
			Baud : in POSITIVE; -- Taktteilerwert für Bps
			sio_txd: out std_logic
		  );
end rs232_out;

architecture Behavioral of rs232_out is

 signal input_puffer: std_logic_vector(8 downto 1);

begin

--######################################
-- Byte an PC senden
--######################################

process (CLK)
 variable Taktteiler : POSITIVE := 1;
 variable state : NATURAL := 9; -- In Wartemodus starten
 variable next_flag_puffer : std_logic := '0';
begin
   if (CLK'event and CLK = '1') then
	
    if Taktteiler >= Baud then
	  Taktteiler := 1;
	  --
	  case state is
		when 0 => -- Start-Bit
		 input_puffer <= input;
		 sio_TxD <= '0';
		 state:=state + 1;
		when 1 to 8 => -- Daten-Bits
		 sio_TxD <= input_puffer(state);
		 state:=state + 1;
		when others =>
		 sio_TxD <= '1'; -- Stop-Bit
		 if (empty_flag = '0') then -- warten auf das nächste Byte
		  state:=0;
		  next_flag_puffer := not next_flag_puffer;
		  next_flag <= next_flag_puffer;
		 end if;
	  end case;
	  --
	 else
	  Taktteiler := Taktteiler + 1;
	 end if;
	 
   end if;
end process;

end Behavioral;