library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity rs232_in is
	Port (
			CLK: 	  in  std_logic;
			output: out std_logic_vector(8 downto 1) := "00000000";
			out_flag: out std_logic := '0';
			Baud : in POSITIVE; -- Taktteilerwert für Bps
			sio_rxd: in std_logic
		  );
end rs232_in;

architecture Behavioral of rs232_in is

	signal RxD_del : std_logic_vector(1 downto 0):= "11";		
	signal Von_PC_Byte: std_logic_vector(8 downto 1):="00000000"; -- Empfangsregister

begin

--######################################
-- Empfang vom PC
--######################################

process(CLK)
 variable Taktteiler : POSITIVE := 1;
 variable State : NATURAL := 0;
 variable busy : std_logic := '0';
 variable out_flag_puffer : std_logic := '0';
begin
 if (CLK'event) and (CLK='1') then
  
  if (RxD_del="10") AND (busy='0') then
   Taktteiler := 1;
	busy := '1';
	State :=  0;	
  elsif Taktteiler >= Baud then  
   Taktteiler := 1;
  else
   Taktteiler := Taktteiler + 1;
  end if;	
	
  if (Taktteiler=(Baud/2)) AND (busy = '1') then
   case State is
    when 0 =>        -- Startbit
	  State:=State+1;
    when 1 to 8 =>  -- Datenbits
     Von_PC_Byte(State) <= sio_rxd;	
	  State:=State+1;
    when others =>
	   output <= Von_PC_Byte;
		out_flag_puffer := not out_flag_puffer;
		out_flag <= out_flag_puffer;
	   busy := '0'; -- warten auf neues Start-Bit
   end case;	 
  end if;

  RxD_del<=RxD_del(0) & sio_rxd;  
 end if;
end process;

end Behavioral;