library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity encod is
	Port (
			input:   in  std_logic_vector(8 downto 1);
		   output:  out std_logic_vector(16 downto 1)
		  );
end encod;

architecture Behavioral of encod is

begin
  
output <= input(8) & (not input(8)) &
			 input(7) & (not input(7)) &
			 input(6) & (not input(6)) &
			 input(5) & (not input(5)) &
			 input(4) & (not input(4)) &
			 input(3) & (not input(3)) &
			 input(2) & (not input(2)) &
			 input(1) & (not input(1));

end Behavioral;