library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity decod is
	Port (
			Input1:   in  std_logic_vector(15 downto 1);
			Input2:   in  std_logic;
		   Output:   out std_logic_vector(8 downto 1);
			Error:    out std_logic
		  );
end decod;

architecture Behavioral of decod is

begin

Output <= Input1(15) &
			 Input1(13) &
			 Input1(11) &
			 Input1( 9) &
			 Input1( 7) &
			 Input1( 5) &
			 Input1( 3) &
			 Input1( 1);
Error <= Not ( 	(Input1(15) xor Input1(14)) AND
						(Input1(13) xor Input1(12)) AND
						(Input1(11) xor Input1(10)) AND
						(Input1( 9) xor Input1( 8)) AND
						(Input1( 7) xor Input1( 6)) AND
						(Input1( 5) xor Input1( 4)) AND
						(Input1( 3) xor Input1( 2)) AND						
						(Input1( 1) xor Input2)		);			  

end Behavioral;