--------------------------------------------------------------------------------
-- a4_temp.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;


entity a4_pwm is
    port(
        clk : in std_logic;
        P10 : in std_logic;  -- Temperatursensor
        P12 : out std_logic; -- Lüfter
        P16 : out std_logic; -- Heizung
        sw : in std_logic_vector(3 downto 0);
        la : out std_logic_vector(0 downto 0);
        led_7seg : out std_logic_vector(7 downto 0);
        an_7seg : out std_logic_vector(3 downto 0)
    );
end entity;

architecture synth of a4_pwm is
    
begin

    -- Anschalten des Lüfters
    P12 <= not sw(1);
    -- Anschalten der Heizung
    P16 <= not sw(0);
    -- LA Ausgang der Daten vom Temperatursensor
    la(0) <= P10;

end architecture;