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-- a2_ps2.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;


entity ps2_top is
    port(
        clk         : in    std_logic;
        ps2_data    : in    std_logic;
        ps2_clk     : in    std_logic;
        la          : out   std_logic_vector(1 downto 0);
        led         : out   std_logic_vector(7 downto 0)
    );
end entity;

architecture synth of ps2_top is
    
    signal ps2_data_sample : std_logic := '0';
    signal ps2_clk_sample : std_logic := '0';
    
    signal Q : std_logic_vector(10 downto 0);

begin

    -- Ausgabe der PS2 Signale auf die LA Pins
    la <= ps2_data & ps2_clk;
    
    process(clk)
        variable cnt : unsigned(8 downto 0) := (others => '0');
    begin
        if rising_edge(clk) then
            -- Takt mit 100 kHz
            if cnt = x"FF" then
                -- Abtasten der Eingangssignale
                ps2_clk_sample <= ps2_clk;
                ps2_data_sample <= ps2_data;
            end if;
        
            cnt := cnt + 1;
        end if;
    end process;
    
    -- Speichern der Empfangsdaten in ein Schieberegister
    process(ps2_clk_sample)
    begin
        if falling_edge(ps2_clk_sample) then
            Q <= ps2_data_sample & Q(10 downto 1);
        end if;
    end process;
    
    led <= Q(8 downto 1);

end architecture;