library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Test_Stack is
    Port ( CLK : in std_logic;
           btn_cod : in std_logic_vector(4 downto 0);
		 sw: in std_logic_vector(4 downto 1);
           led : out std_logic_vector(15 downto 0));
end Test_Stack;

architecture Struktur of Test_Stack is


  	signal BCLK: std_logic; -- Handtakt
	component Handtakt is
       Port ( CLK : in std_logic; 	-- 50 MHz Takt
           btn : in std_logic; 	-- Taster zur Takteingabe
		 BCLK: out std_logic);	-- entprellter Takt
     end component;

	component Stack is
	  port( Takt: in std_logic;
      	 put:  in std_logic;
      	 get:  in std_logic;
      	 full: out std_logic;
      	 empty: out std_logic;
      	 Din:  in std_logic_vector(3 downto 0);
      	 Dout: out std_logic_vector(3 downto 0);
	 	 Fuellstand: out std_logic_vector(4 downto 0));
	end component;

  begin

  Stack_Inst: Stack port map
  	(Takt=>BCLK, 
	 put=>sw(1), get=>sw(2),
	 full=>led(14), empty=>led(15),
	 Din=>btn_cod(3 downto 0),
	 Dout=>led(3 downto 0),
	 Fuellstand => led(12 downto 8));


  Handtakt_Inst: Handtakt port map
  	(CLK=>CLK,
	 btn=>btn_cod(4),
	 BCLK=>BCLK);
	
end  Struktur;