JDF G
// Created by Project Navigator ver 1.0
PROJECT ADU
DESIGN adu
DEVFAM spartan2e
DEVFAMTIME 0
DEVICE xc2s300e
DEVICETIME 0
DEVPKG ft256
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE adu.vhd
DEPASSOC adu Praktikum.ucf
[Normal]
xilxBitgStart_Clk=xstvhd, spartan2e, Implementation.t_bitFile, 1102086620, JTAG Clock
xilxNgdbld_AUL=xstvhd, spartan2e, Implementation.t_placeAndRouteDes, 1102086609, True
[STRATEGY-LIST]
Normal=True