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-- VHDL-Beschreibung für ein NAND-Gatter
-- G. Kemnitz, 05.11.2004
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity my_nand2 is
    Port ( i0 : in std_logic;
           i1 : in std_logic;
           o : out std_logic);
end my_nand2;

architecture Behavioral of my_nand2 is
  begin
    o<=i0 nand i1;
  end Behavioral;