library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity Zahlenschloss is
    Port ( CLK : in std_logic;
           btn_cod : in std_logic_vector(4 downto 0);
           led : out std_logic_vector(15 downto 0);
           seg7an : out std_logic_vector(3 downto 0);
           seg7ca : out std_logic_vector(6 downto 0));
end Zahlenschloss;

architecture Behavioral of Zahlenschloss is
	
	signal BCLK: std_logic;

	component Taktentprellung is
    		Port ( CLK : in std_logic; 	-- 50 MHz Takt
       	       btn : in std_logic; 	-- Taster zur Takteingabe
		   	  BCLK: out std_logic);	-- entprellter Takt
end component;

begin

	inst_Entpr: Taktentprellung
		port map( CLK => CLK,
				btn => btn_cod(4),
				BCLK => BCLK);

--------------------------------------------------------------------
-- nachfolgenden Automaten in Zahlenschlossautomaten ändern
--------------------------------------------------------------------
	process(BCLK)
		variable vState: integer range 0 to 11:=0;
	  begin
		if BCLK'event and BCLK='1' then
			case vState is
				when 0 =>
					if btn_cod(3 downto 0) = x"1" then
						vState:=1;
						seg7an<="0000";
					elsif  btn_cod(3 downto 0) = x"2" then
						vState:=1;
						seg7an<="0001";
						seg7ca<="1110111";
					end if;
				when 1 =>
						vState:=0;
						seg7an<="0001";
						seg7ca<="1110001";
				when others =>
					vState:= 0;
			end case;
		end if;
	  end process;
--------------------------------------------------------------------


end Behavioral;