library ieee;
use ieee.std_logic_1164.all;

use work.Aufgabe1;


entity TB is end entity;

architecture Test of TB is
 signal sw : std_logic_vector(4 downto 1);
 signal led: std_logic;
begin

 Testobjekt: entity Aufgabe1(Struktur) port map(sw => sw, led_2FT => led);

 process
 begin
  wait for 50 ns; sw <= "1001";
  wait for 50 ns; sw <= "1101";
  wait for 50 ns; sw <= "1111";
  wait for 50 ns; sw <= "0101";

  wait;

 end process;

end architecture;