library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Rechnereinheit is
	Port (CLK: 		in std_logic;
		 Operand_2:	in std_logic_vector(3 downto 0);
		 Operation:	in std_logic_vector(3 downto 0);
		 Akku_out:	out std_logic_vector(3 downto 0);
		 cy_out:	    	out std_logic;
		 ProdHigh_out: out std_logic_vector(3 downto 0));
end Rechnereinheit;

architecture Behavioral of Rechnereinheit is

	signal Akku, ProdHigh: std_logic_vector(3 downto 0);
	signal cy: std_logic;
begin
 process(CLK)
	variable Produkt: std_logic_vector(7 downto 0);
	variable Summe: std_logic_vector(4 downto 0);
	variable Differenz: std_logic_vector(4 downto 0);

 begin
   if CLK'event and CLK='1' then
	case Operation is 
      when "0000" =>	   -- Lade Akku
         -- ...
      when "0001" =>	   -- Invertiere Akku
         -- ...
      when "0010" =>	   -- bitweises UND
         -- ...
      when "0011" =>	   -- bitweises ODER
         Akku <= Akku or Operand_2;
      when "0100" =>	   -- Übertragsbit einstellen
	    -- ...
      when "0101" =>	   -- Addition mit Eingangsübertrag
         Summe:= ('0' & Akku) + Operand_2 + cy;
	    Akku<=Summe(3 downto 0);
	    cy<=Summe(4);
      when "0110" =>	   -- Subtraktion mit Eingangsübertrag
         -- ...
      when "0111" =>	   -- Multiplikation
         -- ...
      when others =>
         null;		   -- leere Anweisung
      end case;
	end if;
    end process;
 
-- kombinatorische Ausgabe
    -- ...  


end Behavioral;