library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Aufgabe7 is
    Port ( CLK : in std_logic;
           btn_cod : in std_logic_vector(4 downto 0);
           led : out std_logic_vector(15 downto 0));
end Aufgabe7;

architecture Behavioral of Aufgabe7 is
	signal Q: std_logic_vector(26 downto 0);
	signal AmpelTakt: std_logic;
	constant cBTN0: std_logic_vector(4 downto 0):="10000";

begin

-------------------------------------------------------
--		Taktteiler
-------------------------------------------------------
process(CLK)
	begin
		if CLK'event and CLK='1' then
			Q<=Q+'1';
		end if;
	end process;
-------------------------------------------------------

 	AmpelTakt <= Q(26);
	led(15)   <= Q(26);

-------------------------------------------------------
--	nachfolgenden Automaten in Ampelautomat ändern
-------------------------------------------------------
process(AmpelTakt)
		-- Auf die erforderliche Zustandszahl anpassen
		variable vState: integer range 0 to 1:=0;
	begin
		if AmpelTakt'event and AmpelTakt='1' then
			case vState is
				when 0 =>
					led(1 downto 0) <="01";
					if btn_cod=cBTN0 then
						vState:=1;
					end if;
				when 1 =>
					led(1 downto 0) <="10";
					vState:=0;
				when others =>
					vState:=0;
			end case;
		end if;
	end process;
-------------------------------------------------------
 

end Behavioral;