library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Aufgabe6 is
    Port ( CLK : in std_logic;	 				-- Takt 50 MHz
           sw : in std_logic_vector(4 downto 1);		-- Schalter: 2. Operand)
           btn_cod : in std_logic_vector(4 downto 0);	-- Taster: Operationsauswahl)
           led : out std_logic_vector(15 downto 0));	-- Leuchtdioden: Ausgabe
end Aufgabe6;

architecture Behavioral of Aufgabe6 is

signal Akku: std_logic_vector(3 downto 0); 	  -- Akkumulator (Ergebnis + 1. Operand)
signal ProdHigh: std_logic_vector(3 downto 0); -- oberer Produktvektor
signal cy: std_logic;	                      -- Übertrag
signal BCLK: std_logic;					  -- entprellter Handtakt

-- Einbindung einer Schaltung zur Taktentprellung
component Taktentprellung is
    Port ( CLK : in std_logic;   -- 50 MHz Takt
           btn : in std_logic;   -- Tastersignal
		 BCLK: out std_logic); -- entprelltes Tastersignal
end component;

-- Einbindung der Recheneinheit
component Rechnereinheit is
	Port (CLK: 		in std_logic;
		 Operand_2:	in std_logic_vector(3 downto 0);
		 Operation:	in std_logic_vector(3 downto 0);
		 Akku_out:	out std_logic_vector(3 downto 0);
		 cy_out:	    	out std_logic;
		 ProdHigh_out: out std_logic_vector(3 downto 0));
end component;

begin

inst_TE: Taktentprellung port map
    		(CLK =>CLk,           -- 50 MHz Takt
           btn => btn_cod(4),   -- Tastersignal
		 BCLK => BCLK);       -- entprelltes Tastersignal

inst_RE: Rechnereinheit port map
	(CLK => BCLK,
	 Operand_2 => sw,
	 Operation => btn_cod(3 downto 0),
	 Akku_out => led(3 downto 0),
	 cy_out => led(4),
	 ProdHigh_out => led(11 downto 8));

-- Zähler zum Test des Handtaktes
process(BCLK)
	variable vCt: std_logic_vector(3 downto 0);
  begin
    if BCLK'event and BCLK='1' then
    	 vCt:= vCt + '1';
	 led(15 downto 12) <= vCt;
    end if;
    end process;
end Behavioral;