library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Aufgabe4 is
    Port ( CLK : in std_logic;
           btn_2FT : in std_logic;
           sw : in std_logic_vector(1 downto 1);
           led : out std_logic_vector(7 downto 0));
end Aufgabe4;

architecture a4 of Aufgabe4 is
	constant Init: std_logic_vector(7 downto 0):=x"19";
	signal state: std_logic_vector(7 downto 0):=Init; 
	-- signal Taktteiler: std_logic_vector(25 downto 0);
	-- signal CLK_1Hz: std_logic;
begin

	process(CLK, btn_2FT)
	  begin
		if btn_2FT='1' then
			state<=Init;
		
		elsif (CLK'event and CLK='1' and sw(1)='1') then
			state<=(state(6 downto 0) & '0') xor
				  ('0' & state(7 downto 1)) xor
				  (state and "10101011");
		end if;
	end process;

	led<=state;


end a4;