library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Aufgabe3 is
    Port ( CLK : in std_logic;
           btn_2FT : in std_logic;
           led : out std_logic_vector(15 downto 0));
end Aufgabe3;

architecture Behavioral of Aufgabe3 is
	signal Q: std_logic_vector(31 downto 0);
	signal btn_del: std_logic_vector(1 downto 0);
	signal Clk20Hz, BCLK: std_logic;
	signal Ausg: std_logic_vector(3 downto 0);

begin
	-- Process für den Taktteiler
	   process(CLK)
	   	begin
			if CLK'event and CLK='1' then
				Q <= Q +'1';
			end if;
		end process;

		-- ...

	-- Process für die Tastenentprellung
		process(Clk20Hz)
		  begin
			if Clk20Hz'event and Clk20Hz='1' then
			-- ...		
			end if;
		end process;

	-- Process zum Zählen, wie oft die Taste gedrückt ist
		process(BCLK)
		  begin
			if BCLK'event and BCLK='1' then
				-- ...
			end if;
		end process;
		-- ...

end Behavioral;