-- G. Kemnitz: Technische Informatik 
-- Band 2: Entwurf digitaler Schaltungen
-- 1.3.5 Zusammenfassung und Uebungsaufgaben
--
-- Lösung zu Aufgabe 1.10
---------------------------------------------------------------


library ieee;
use ieee.std_logic_1164.all;

entity LsgAfgHazard is end entity;

architecture a of LsgAfgHazard is
    signal x0, x2, z0, z1: std_logic:='0';
    signal x1, z2, y: std_logic:='1';
begin

 G1: z0 <= not x1 after 1 ns;
 G2: z1 <= x0 and z0 after 2 ns;
 G3: z2 <= z0 xnor x2 after 4 ns;
 G4: y <= z1 nand z2 after 1.5 ns;

 Ex0: x0 <= '1' after  1 ns;
 Ex1: x1 <= '0' after  2 ns;
 Ex2: x2 <= '1' after 10 ns;
 
end architecture;