-- G. Kemnitz: Technische Informatik 
-- Band 2: Entwurf digitaler Schaltungen
-- 1.5.5 Zusammenfassung und Uebungsaufgaben
--
-- Aufgabe 1.17
---------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity Lsg2Tasten is end entity;

architecture Test of Lsg2Tasten is
 signal x, x_del, x_del2, y: std_logic_vector(1 downto 0);
 signal T: std_logic;
begin

 process(T)
 begin

  if rising_edge(T) then
   x_del  <= x;
   x_del2 <= x_del;
  end if;
 end process;

 y(0) <= not x_del(0) and x_del2(0) and x_del(1);
 y(1) <= not x_del(1) and x_del2(1) and x_del(0);

 Taktprozess: process
 begin
  if now > 20 ns then wait; end if;
  wait for 0.54 ns; T<='1';
  wait for 0.54 ns; T<='0';
 end process;

 x(0) <= '1', '0' after 3 ns, '1' after 5 ns, '0' after 12 ns, '1' after 15 ns;
 x(1) <= '1', '0' after 8 ns, '1' after 10 ns, '0' after 13 ns, '1' after 18 ns;

end architecture;