-- G. Kemnitz: Technische Informatik 
-- Band 2: Entwurf digitaler Schaltungen
-- 1.3.5 Zusammenfassung und Uebungsaufgaben
--
-- Kontrolle der Lösung zu Aufgabe 1.11
---------------------------------------------------------------



library ieee;
use ieee.std_logic_1164.all;

entity AfgVerzMod is end entity;
architecture a of AfgVerzMod is
 signal y: std_logic;
begin

 process
 begin
  y <= '0', 'X' after 3 ns, '1' after 7 ns,  'X' after 8 ns, '1' after 10 ns,  '0' after 11  
    ns, '1' after 13 ns, '1' after 15 ns, 'X' after 18 ns, '0' after 20 ns;

   wait for 5 ns;

   y <= '1' after 12 ns;
-- y <= transport '1' after 12 ns;
-- y <= reject 8 ns inertial '1' after 12 ns;

  wait;
 end process;
end architecture;