-- G. Kemnitz: Technische Informatik 
-- Band 2: Entwurf digitaler Schaltungen
-- 1.4.6 Zusammenfassung und Uebungsaufgaben
--
-- Lösung zu Aufgabe 1.14
---------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity AfgKombReg is end entity;

architecture Test of AfgKombReg is
 signal x0, x1, x2, y, T: std_logic;
 constant th1: delay_length:= 0.4 ns;
 constant td1: delay_length:= 1.2 ns;
 constant th2: delay_length:= 0.6 ns;
 constant td2: delay_length:= 1.0 ns;
 constant ts:  delay_length:= 0.5 ns;
 constant thr: delay_length:= 0.2 ns;
 constant tdr: delay_length:= 0.4 ns;
 
begin

 process(T)
 begin
  if rising_edge(T) then
   if x0'delayed(th1+th2)'last_event>td1+td2+ts-th1-th2 and 
     x1'delayed(th1+th2)'last_event>td1+td2+ts-th1-th2 and
     x2'delayed(th2)'last_event>td2+ts-th2 then
    y <= 'X' after thr, (x0 xor x1) and x2 after tdr;
   else
    y <= 'X' after thr;
   end if;
  end if;
 end process;

 Taktprozess: process
 begin
  if now > 20 ns then wait; end if;
  wait for 2 ns; T<='1';
  wait for 2 ns; T<='0';
 end process;

 x0 <= '0', '1' after 4 ns;
 x1 <= '1', '0' after 7 ns;
 x2 <= '1', '0' after 13 ns, '1' after 16 ns;

end architecture;