-- G. Kemnitz: Technische Informatik 
-- Band 2: Entwurf digitaler Schaltungen
-- 4.2.5 Simulation mit geschalteten Transistorbreiten
--
-- Simulationsmodell eines Komplexgatters mit geschalteten 
-- Transistorbreiten
----------------------------------------------------------------



library ieee;
use ieee.std_logic_1164.all;

library Tuc;
use Tuc.Ausgabe.all;

use work.bRel_pack.all;

entity KG10T is
 generic(tau: delay_length:=100 ps;
  bn1, bn2, bn3, bn4, bn5: real:= 1.0;
  bp1, bp2, bp3, bp4, bp5: real:= 1.0);
 port( x1, x2, x3, x4, x5: in std_logic;
  y: out std_logic);
end entity;

architecture Sim of KG10T is
   signal yy: std_logic;
 begin
  process(x1, x2, x3, x4, x5)
   variable n, p: tRelB;
  begin

   p := ((To_RelB(not x1, bn1) or To_RelB(not x2, bn2)) 
           and  To_RelB(not x3, bn3)) or
           (To_RelB(not x4, bn4) and To_RelB(not x5, bn5));

   n := ((To_RelB(x1, bn1) and To_RelB(x2, bn2)) 
           or To_RelB(x3, bn3)) 
           and (To_RelB(x4, bn4) or To_RelB(x5, bn5));

   write("   p=" & str(p) & " n=" & str(n));

   if yy='0' and p.bmax>0.0 then 
    yy<='X' after (2.0/p.bmax)*tau; 
    write("   y<='X' after " & str((2.0/p.bmax)*tau));
   elsif yy='1' and n.bmax>0.0 then 
    yy<='X' after (1.0/n.bmax)*tau; 
    write("   y<='X' after " & str((1.0/n.bmax)*tau));
   end if;

   if n.bmax=0.0 and p.bmin > 0.0 then
    yy <= transport '1' after (2.0/p.bmin)*tau;
    write("   y<= transport '1' after " & str((2.0/p.bmin)*tau));
   elsif p.bmax=0.0 and n.bmin > 0.0 then
    yy <= transport '0' after (1.0/n.bmin)*tau;
    write("   y<= transport '0' after " & str((1.0/n.bmin)*tau));
   end if;
 end process;
 y <= yy;

end architecture;