-- G. Kemnitz: Technische Informatik 
-- Band 2: Entwurf digitaler Schaltungen
-- 2.2.4 KV-Diagramme

-- Testrahmen für die 7-Segment-Decoder-Beschreibungen
---------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

library Tuc;
use Tuc.Ausgabe.all;

entity TestSeg7 is end entity;

architecture a of TestSeg7 is
 signal x: std_logic_vector(3 downto 0);
 signal y1, y2: std_logic_vector(6 downto 0);
begin

 Version_FU: entity work.Seg7Dec(FU) port map(x, y1); 
 Version_KV: entity work.Seg7Dec(KV) port map(x, y2); 

 Testprozess: process
 begin
  x<="0000"; wait for 1 ns; write("x=" &str(x) & " y1=" & str(y1) & " y2=" & str(y2));
  x<="0001"; wait for 1 ns; write("x=" &str(x) & " y1=" & str(y1) & " y2=" & str(y2));
  x<="0010"; wait for 1 ns; write("x=" &str(x) & " y1=" & str(y1) & " y2=" & str(y2));
  x<="0011"; wait for 1 ns; write("x=" &str(x) & " y1=" & str(y1) & " y2=" & str(y2));
  x<="0100"; wait for 1 ns; write("x=" &str(x) & " y1=" & str(y1) & " y2=" & str(y2));
  x<="0101"; wait for 1 ns; write("x=" &str(x) & " y1=" & str(y1) & " y2=" & str(y2));
  x<="0110"; wait for 1 ns; write("x=" &str(x) & " y1=" & str(y1) & " y2=" & str(y2));
  x<="0111"; wait for 1 ns; write("x=" &str(x) & " y1=" & str(y1) & " y2=" & str(y2));
  x<="1000"; wait for 1 ns; write("x=" &str(x) & " y1=" & str(y1) & " y2=" & str(y2));
  x<="1001"; wait for 1 ns; write("x=" &str(x) & " y1=" & str(y1) & " y2=" & str(y2));
  x<="1010"; wait for 1 ns; write("x=" &str(x) & " y1=" & str(y1) & " y2=" & str(y2));
  x<="1011"; wait for 1 ns; write("x=" &str(x) & " y1=" & str(y1) & " y2=" & str(y2));
  x<="1100"; wait for 1 ns; write("x=" &str(x) & " y1=" & str(y1) & " y2=" & str(y2));
  x<="1101"; wait for 1 ns; write("x=" &str(x) & " y1=" & str(y1) & " y2=" & str(y2));
  x<="1110"; wait for 1 ns; write("x=" &str(x) & " y1=" & str(y1) & " y2=" & str(y2));
  x<="1111"; wait for 1 ns; write("x=" &str(x) & " y1=" & str(y1) & " y2=" & str(y2));
  wait;
 end process;
end architecture;