-- G. Kemnitz: Technische Informatik 
-- Band 2: Entwurf digitaler Schaltungen
-- Abschnitt 2.6.9 Zusammenfassung und Uebungsaufgaben
--
-- Aufgabe 2.20 (Matrixmultiplizierer für vorzeichenbehaftete Zahlen)
-- Aufgabe 2.21 (Multiplizierer für vorzeichenbehaftete Zahlen
-- mit Multiplikation der Beträge
--------------------------------------------------------


library ieee;
use ieee.std_logic_1164.all;

library Tuc;
use Tuc.Numeric_sim.all;

library Tuc;
use Tuc.Numeric_Sim.all;
use Tuc.Ausgabe.all;

entity SignedMult is 
 port(a, b: in tSigned(3 downto 0);
    y: out tSigned(7 downto 0));
end entity;

-- Strukturbeschreibung zur Kontrolle der Lösung von Aufgabe 2.20
architecture StrucSVA of SignedMult is
 signal p: std_logic_vector(9 downto 0); -- positiv bewertete Zwischenergebnisse
 signal n: std_logic_vector(6 downto 0); -- negativ bewertete Zwischenergebnisse
 signal pr00, pr01, pr02, pr03, pr10, pr11, pr12, pr13, 
        pr20, pr21, pr22, pr23, pr30, pr31, pr32, pr33: std_logic;
begin
 pr00<=a(0) and b(0); pr01<=a(0) and b(1); pr02<=a(0) and b(2); pr03<=a(0) and b(3);
 pr10<=a(1) and b(0); pr11<=a(1) and b(1); pr12<=a(1) and b(2); pr13<=a(1) and b(3);
 pr20<=a(2) and b(0); pr21<=a(2) and b(1); pr22<=a(2) and b(2); pr23<=a(2) and b(3);
 pr30<=a(3) and b(0); pr31<=a(3) and b(1); pr32<=a(3) and b(2); pr33<=a(3) and b(3);

 y(0) <= pr00;
 HA10: entity work.HA0(Verh) port map(a=>pr10, b =>pr01,           s =>y(1), co =>p(0));
 VA11: entity work.VA0(Verh) port map(a=>p(0), b =>pr20, c =>pr11, s =>p(1), co =>p(2));
 VA12: entity work.VA1(Verh) port map(a=>p(2), b =>pr21, nc=>pr30, ns=>n(0), co =>p(3));
 HA13: entity work.HA1(Verh) port map(a=>p(3), nb=>pr31,           s =>p(4), nco=>n(1));

 HA21: entity work.HA0(Verh) port map(a=>p(1), b =>pr02,           s =>y(2), co =>p(5));
 VA22: entity work.VA1(Verh) port map(a=>p(5), b =>pr12, nc=>n(0), ns=>n(2), co =>p(6));
 VA23: entity work.VA0(Verh) port map(a=>p(6), b =>p(4), c =>pr22, s =>p(7), co =>p(8));
 VA24: entity work.VA2(Verh) port map(a=>p(8), nb=>n(1), nc=>pr32, s =>p(9), nco=>n(3));

 HA32: entity work.HA2(Verh) port map(         na=>n(2), nb=>pr03, s=>y(3), nco=>n(4));
 VA33: entity work.VA2(Verh) port map(a=>p(7), nb=>n(4), nc=>pr13, s=>y(4), nco=>n(5));
 VA34: entity work.VA2(Verh) port map(a=>p(9), nb=>n(5), nc=>pr23, s=>y(5), nco=>n(6));
 VA35: entity work.VA2(Verh) port map(a=>pr33, nb=>n(6), nc=>n(3), s=>y(6), nco=>y(7));
end architecture;

-- Lösung von Aufgabe 2.22

architecture Mux of SignedMult is
begin

 process(a, b)
  variable va, vb: tUnsigned(2 downto 0);
  variable vy: tUnsigned(5 downto 0);
 begin
  if a(3)='1' then
   va := tUnsigned(not a(2 downto 0))+"1";
  else
   va := tUnsigned(a(2 downto 0));
  end if;
  if b(3)='1' then
   vb := tUnsigned(not b(2 downto 0))+"1";
  else
   vb := tUnsigned(b(2 downto 0));
  end if;
  vy := va * vb;
  if (a(3) = b(3)) or vy="000000" then
   y <=  "00" & tSigned(vy);
  else y <= "11" & tSigned((not vy) +"1");
  end if;
 end process;
end architecture;