-- G. Kemnitz: Technische Informatik 
-- Band 2: Entwurf digitaler Schaltungen
-- Abschnitt 2.6.5 Dividierer
--
-- Dialogtest für der Divisionsalgorithmus
--------------------------------------------------------


library ieee;
use ieee.std_logic_1164.all;

library Tuc;
use Tuc.Numeric_Sim.all;
use Tuc.Ausgabe.all;
use Tuc.Eingabe.all;
use Tuc.StopSim_pack.all;

entity SerDivAlg is end entity;

architecture Test of SerDivAlg is
 signal Rest, q: tUnsigned(3 downto 0);
 signal Subtr: tUnsigned(6 downto 0);
 signal Start, busy, T: std_logic;
begin

Taktgenerator: TaktGen(T, 10 ns);

-- Startsignal 
Start <= '1' after 30 ns, '0' after 63 ns, '1' after 107 ns;

Testprozess: process
  variable d: tUnsigned(6 downto 0);
  variable Divident, Divisor: tUnsigned(3 downto 0);
 begin
  wait until rising_edge(T) and Start='1'; 
  read("Eingabe Divident (4 Bit): ", Divident); 
  read("Eingabe Divisor (4 Bit): ", Divisor);
  Rest<= Divident;
  Subtr<=Divisor & "000";
  busy<='1'; 

  wait until rising_edge(T);

  for i in 0 to 3 loop
   d := Rest - Subtr;
   Subtr <= '0' & Subtr(6 downto 1);
   q <= q(2 downto 0) & (not d(6));
   if d(6) = '0' then
    Rest <= d(3 downto 0);
   end if;  
  wait until rising_edge(T);
  end loop;
  write(rechts(str(now),8) & " Quotient= " & str(q) & " Rest=" & str(Rest)); 
  busy<='0'; 
 end process;

 

end architecture;