-- G. Kemnitz: Technische Informatik 
-- Band 2: Entwurf digitaler Schaltungen
-- Abschnitt 2.6.5 Dividierer
--
-- (Aufgabe 2.21) des seriellen Dividierers
--------------------------------------------------------


library ieee;
use ieee.std_logic_1164.all;

library Tuc;
use Tuc.Numeric_Sim.all;
use Tuc.Ausgabe.all;

entity SerDiv is 
 port(Dividend, Divisor: in tUnsigned(3 downto 0);
    T, Start: in std_logic;
    Quotient, Rest_out: out tUnsigned(3 downto 0);
    busy_out: out std_logic);
end entity;

architecture Synth of SerDiv is
 signal Rest, q: tUnsigned(3 downto 0);
 signal Subtr: tUnsigned(6 downto 0);
 signal busy: std_logic;
 signal ct: tUnsigned(1 downto 0);
begin

 process(T)
  variable d: tUnsigned(6 downto 0);
 begin

  if rising_edge(T) then
   if busy='1'then
    d := Rest - Subtr;
    Subtr <= '0'&Subtr(6 downto 1);
    q <= q(2 downto 0) & (not d(6));
    ct<=ct+"1";
    if d(6) = '0' then
     Rest <= d(3 downto 0);
    end if;  
    if ct="11" then
     busy<='0'; 
    end if;
   elsif Start='1' then 
    Rest<=Dividend;
    Subtr<=Divisor& "000";
    busy<='1'; 
    Ct<="00";
   end if;
  end if;
 end process;

 Quotient <= q;
 Rest_out <= Rest;
 busy_out<=busy;
end architecture;