-- G. Kemnitz: Technische Informatik 
-- Band 2: Entwurf digitaler Schaltungen
-- Abschnitt 2.5.2 Serieller Addierer
--
-- beide Beschreibungsversionen des seriellen Addierers
--------------------------------------------------------


library ieee;
use ieee.std_logic_1164.all;

library Tuc;
use Tuc.Numeric_Sim.all;
use Tuc.Ausgabe.all;

entity SerAdd is 
 port(x1, x2: in std_logic_vector(3 downto 0);
    T, cin, Start: in std_logic;
    y: out std_logic_vector(3 downto 0);
    cout, busy_out: out std_logic);
end entity;

-- Ablaufbeschreibung
architecture Sim of SerAdd is
 signal c, busy: std_logic;
 signal a, b, s: std_logic_vector(3 downto 0);
begin

 process 
 begin
  busy<='0';
  wait until Start='1' and rising_edge(T);
  busy<='1';
  c<=cin; a<=x1; b<=x2;
  wait until rising_edge(T);
  for i in 0 to 3 loop
   s(i)<=a(i) xor b(i) xor c;
   c<=(a(i) and b(i)) or (a(i) and c) or (b(i) and c);
   wait until rising_edge(T);
  end loop;

 end process;
 y<=s; busy_out<=busy;
end architecture;


-- Synthesebeschreibung
architecture Synth of SerAdd is
 signal c, busy: std_logic;
 signal a, b, s: std_logic_vector(3 downto 0);
 signal ct: tUnsigned(1 downto 0);
begin

 process(T) 
 begin
  if rising_edge(T) then
   if busy='1' then
    s<=(a(0) xor b(0) xor c) & s(3 downto 1);
    c<=(a(0) and b(0)) or (a(0) and c) or (b(0) and c);
    a<='0' & a(3 downto 1); b<='0' & b(3 downto 1);
    ct <= ct + "1"; 
    if ct = "11" then
     busy<= '0';
    end if;
   elsif Start='1' then
    ct<="00"; busy<='1'; c<=cin; a<= x1; b<= x2;
   end if;
  end if;
 end process;

 y<=s; busy_out<=busy;

end architecture;