-- G. Kemnitz: Technische Informatik 
-- Band 2: Entwurf digitaler Schaltungen
-- 2.2.4 KV-Diagramme

-- Mehrversionsbeschreibung für einen 7-Segment-Decoder
-- * architecture FU -- Beschreibung mit einer Auswahlanweisung
-- * architecture KV -- Beschreibung mit den über KV-Diagramme berechneten 
--                      bitorientierten Ausdrücken
---------------------------------------------------------------



library ieee;
use ieee.std_logic_1164.all;

entity Seg7Dec is 
 port(x: in  std_logic_vector(3 downto 0);
      y: out std_logic_vector(6 downto 0));
end entity;

architecture FU of Seg7Dec is
begin
 process(x)
 begin
  case x is
   when "0000"   => y <=  "0111111";
   when "0001"   => y <=  "0000110";
   when "0010"   => y <=  "1011011";
   when "0011"   => y <=  "1001111";
   when "0100"   => y <=  "1100110";
   when "0101"   => y <=  "1101101";
   when "0110"   => y <=  "1111101";
   when "0111"   => y <=  "0000111";
   when "1000"   => y <=  "1111111";
   when "1001"   => y <=  "1101111";
   when others 	 => y <=  "-------";
  end case;
 end process;
end architecture;

architecture KV of Seg7Dec is
begin
 process(x)
  variable a,b,c,d,e,f,g,h,i,j: std_logic;
 begin
  a := not x(3) and not x(2) and not x(1) and x(0);
  b := x(2) and not x(1) and not x(0);
  c := x(2) and not x(1) and x(0);
  d := x(2) and x(1) and not x(0);
  e := not x(2) and x(1) and not x(0);
  f := x(2) and x(1) and x(0);
  g := x(0);
  h := not x(3) and not x(2) and x(1);
  i := x(1) and x(0);
  j := not x(3) and not x(2) and not x(1);

  y(0) <= not(a or b);-- after 1.3 ns;
  y(1) <= not(c or d);-- after 1.2 ns;
  y(2) <= not e;-- after 0.8 ns;
  y(3) <= not(a or b or f);-- after 1.9 ns;
  y(4) <= not(b or g);-- after 1.2 ns;
  y(5) <= not(a or h or i);-- after 3.1 ns;
  y(6) <= not(f or j);-- after 1.1 ns;

 end process;

end architecture;