-- G. Kemnitz: Technische Informatik 
-- Band 2: Entwurf digitaler Schaltungen
-- Abschnitt 2.5.1 Ripple-Addierer
--
-- Funktionsmodell des Ripple-Addierers (Abb. 2.81)
--------------------------------------------------------


library ieee;
use ieee.std_logic_1164.all;

library Tuc;
use Tuc.Ausgabe.all;

entity RippleAdd is end entity;

architecture Verh of RippleAdd is
 signal a,b,s:std_logic_vector(3 downto 0);
 signal cin, cout: std_logic;

begin
 
 process(a, b, cin)
  variable c: std_logic;
 begin
  c:=cin;
  for i in 0 to 3 loop
   s(i)<=a(i) xor b(i) xor c;
   c:=(a(i) and b(i)) or (a(i) and c) or (b(i) and c);
  end loop;
  cout<=c;
 end process;

 process
 begin
  cin<='0'; a <= "0110"; b <= "1101"; wait for 10 ns;
  write( " cin=" & str(cin) & " a=" & str(a) & " b=" & str(b) & " || s=" & str(s) & " cout=" & str(cout));
  cin<='1'; a <= "0110"; b <= "1101"; wait for 10 ns;
  write( " cin=" & str(cin) & " a=" & str(a) & " b=" & str(b) & " || s=" & str(s) & " cout=" & str(cout));
  cin<='0'; a <= "1110"; b <= "0101"; wait for 10 ns;
  write( " cin=" & str(cin) & " a=" & str(a) & " b=" & str(b) & " || s=" & str(s) & " cout=" & str(cout));
  wait;
 end process;

end architecture;