-- G. Kemnitz: Technische Informatik -- Band 2: Entwurf digitaler Schaltungen -- Abschnitt 2.5.4 Hierarchischer Addierer -- -- Erschöpfender Test des hierarchischen Addierers in -- Abb. 2.87 -------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library Tuc; use Tuc.Numeric_Sim.all; use Tuc.Ausgabe.all; use work.HiAdd_pack.all; entity HiAdd is end entity; architecture Test of HiAdd is begin process variable pg0, pg1, pg2, pg3, pg4, pg5, pg6, pg7: tPG; variable pg01, pg23, pg34, pg45, pg67, pg0_3, pg4_7: tPG; variable pg0_5, pg0_7, pg0_2, pg0_4, pg0_6: tPG; variable a, b, p, g, s, c: tUnsigned(7 downto 0); variable cout: std_logic; begin for idx_a in 0 to 255 loop for idx_b in 0 to 255 loop for idx_c in 0 to 1 loop a := to_tUnsigned(idx_a, 8); b := to_tUnsigned(idx_b, 8); c(0 downto 0) := to_tUnsigned(idx_c, 1); for idx in 0 to 7 loop p(idx) := a(idx) xor b(idx); g(idx) := a(idx) and b(idx); end loop; pg0 := (p=>p(0), g=>g(0)); pg1 := (p=>p(1), g=>g(1)); pg2 := (p=>p(2), g=>g(2)); pg3 := (p=>p(3), g=>g(3)); pg4 := (p=>p(4), g=>g(4)); pg5 := (p=>p(5), g=>g(5)); pg6 := (p=>p(6), g=>g(6)); pg7 := (p=>p(7), g=>g(7)); pg01 := OpPG(pg0, pg1); pg23 := OpPG(pg2, pg3); pg45 := OpPG(pg4, pg5); pg67 := OpPG(pg6, pg7); pg0_3 := OpPG(pg01, pg23); pg4_7 := OpPG(pg45, pg67); pg0_5 := OpPG(pg0_3, pg45); pg0_7 := OpPG(pg0_3, pg4_7); pg0_2 := OpPG(pg01, pg2); pg0_4 := OpPG(pg0_3, pg4); pg0_6 := OpPG(pg0_5, pg6); c(1) := g(0) or (c(0) and p(0)); c(2) := pg01.g or (c(0) and pg01.p); c(3) := pg0_2.g or (c(0) and pg0_2.p); c(4) := pg0_3.g or (c(0) and pg0_3.p); c(5) := pg0_4.g or (c(0) and pg0_4.p); c(6) := pg0_5.g or (c(0) and pg0_5.p); c(7) := pg0_6.g or (c(0) and pg0_6.p); cout := pg0_7.g or (c(0) and pg0_7.p); for idx in 0 to 7 loop s(idx) := c(idx) xor p(idx); end loop; if (('0' & a) + b + c(0 downto 0)) /= cout & s then write("a=" & str(a, 'd') & " b=" & str(b, 'd') & " c(0)=" & str(c(0)) & " || cout=" & str(cout) & " s=" & str(s, 'd')); end if; end loop; end loop; end loop; write("Testende"); wait; end process; end architecture;