-- G. Kemnitz: Technische Informatik 
-- Band 2: Entwurf digitaler Schaltungen
-- Abschnitt 2.6.5 Dividierer
--
-- Dialogtest für der Divisionsalgorithmus
--------------------------------------------------------


library ieee;
use ieee.std_logic_1164.all;

library Tuc;
use Tuc.Numeric_Sim.all;
use Tuc.Ausgabe.all;
use Tuc.Eingabe.all;

entity DivAlg is end entity;

architecture Test of DivAlg is
begin

 Testprozess: process
  variable Rest, q: tUnsigned(3 downto 0);
  variable Subtr, d: tUnsigned(6 downto 0);
 begin
  read("Eingabe Dividend (4 Bit): ", Rest); 
  read("Eingabe Divisor (4 Bit): ", Subtr(6 downto 3));
  Subtr(2 downto 0):="000";
  for i in 3 downto 0 loop
   d := Rest - Subtr;
   Subtr := Subtr srl 1;
   q(i) := not d(6);
   if d(6) = '0' then Rest := d(3 downto 0); end if;  
  end loop;
  write("Quotient= " & str(q) & " Rest=" & str(Rest)); 
 end process;

end architecture;