-- G. Kemnitz: Technische Informatik 
-- Band 2: Entwurf digitaler Schaltungen
-- Abschnitt 2.1.7 Zusammenfassung und Uebungsaufgaben
--
-- Aufgabe 2.5
--------------------------------------------------------


library ieee;
use ieee.std_logic_1164.all;

library Tuc;
use Tuc.Numeric_Synth.all;

entity AfgSynthAutomat is
 port(T, I: in std_logic;
   x: in std_logic_vector(1 downto 0);
   y: out std_logic_vector(1 downto 0));
end entity;

architecture Synth of AfgSynthAutomat is
 signal s_next, s: std_logic_vector(1 downto 0);
begin

 process(s, x)
  variable sx: std_logic_vector(3 downto 0);
 begin
  sx := s & x;
  case sx is
   when "00"&"00" | "01"&"01" | "10"&"10" => s_next <= "01";
   when "01"&"00" | "10"&"01" | "11"&"10" => s_next <= "10";
   when "10"&"00" | "11"&"01" | "00"&"10" => s_next <= "11";
   when others  => s_next <= "00";
  end case;
 end process;

 process(I, T)
 begin
  if I='1' then
   s <= "00";
  elsif rising_edge(T) then
   s <= s_next;
  end if;
 end process;
 y <= s_next;
end architecture;