-- G. Kemnitz: Technische Informatik 
-- Band 2: Entwurf digitaler Schaltungen
-- Abschnitt 2.1.7 Zusammenfassung und Uebungsaufgaben
--
-- Aufgabe 2.6
--------------------------------------------------------


library ieee;
use ieee.std_logic_1164.all;

library Tuc;
use Tuc.Numeric_Synth.all;

entity AfgSynthALU2 is
 port(T: in std_logic;
     x: in tUnsigned(3 downto 0);
  op: in std_logic_vector(1 downto 0);
  y: out tUnsigned(3 downto 0));
end entity;

architecture Synth of AfgSynthALU2 is
 signal tmp, acc: tUnsigned(3 downto 0);
begin
 process(T)
 begin
  if rising_edge(T) then
   case op is
    when "00" => acc <= x;
    when "01" => acc <= acc + tmp;
    when "10" => acc <= acc - tmp;
    when others => null;
   end case;
  end if;
  tmp <= x;
 end process;

 y <= acc;
end architecture;