---------------------------------------------------------------------
-- a5_vga.vhd
---------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity a5_vga is 
    port(
        clk : in std_logic;
        hs :  out std_logic; -- horizontal sync impuls (line)
        vs :  out std_logic; -- vertical sync impuls (image)
        rgb : out std_logic_vector(2 downto 0) -- RGB-Signal
    );
end entity;

architecture synth of a5_vga is

    signal Takt25MHz : std_logic;
    signal hCounter : integer range 0 to 799 := 0;
    signal vCounter : integer range 0 to 520 := 0;
    signal hBlack : std_logic := '1';
    signal vBlack : std_logic := '1';

    -- display corlors
    constant schwarz :  std_logic_vector(2 downto 0) := "000";
    constant rot :      std_logic_vector(2 downto 0) := "100";
    constant gruen :    std_logic_vector(2 downto 0) := "010";
    constant blau :     std_logic_vector(2 downto 0) := "001";
    constant gelb :     std_logic_vector(2 downto 0) := "110";
    constant cyan :     std_logic_vector(2 downto 0) := "011";
    constant violett :  std_logic_vector(2 downto 0) := "101";
    constant weis :     std_logic_vector(2 downto 0) := "111";

    -- read only memory initialized with a pixel graphic (1 bit per pixel)
    type rom_type is array (0 to 31) of std_logic_vector (31 downto 0); 
    constant Bild : rom_type := (
        "11111111111111111111111111111111",  -- Zeile 0
        "10000000000000000000000000000001",  -- Zeile 1
        "10000000000000011111100000000001",  -- Zeile 2
        "10000000000001110000111000000001",  -- Zeile 3
        "10000000000011000000001100000001",  -- Zeile 4
        "10000001000100000000000010000001",  -- Zeile 5
        "10000000110000000000000000001001",  -- Zeile 6
        "10000000011100000000000000010001",  -- Zeile 7
        "10000000001111000000000000100001",  -- Zeile 8
        "10000000000011111000000011000001",  -- Zeile 9
        "10000000000000000000000100000001",  -- Zeile 10
        "10000000000000000000000010000001",  -- Zeile 11
        "10000000000111000000001100000001",  -- Zeile 12
        "10000000001000100001110000000001",  -- Zeile 13
        "10000000000000011110000000000001",  -- Zeile 14
        "10000000000000000000000000000001",  -- Zeile 15
        "10000000000000000000000000000001",  -- Zeile 16
        "10000000010000000000000000000001",  -- Zeile 17
        "10000000111000000000000000000001",  -- Zeile 18
        "10000000111000000000000000000001",  -- Zeile 19
        "10000000111110000000000000000001",  -- Zeile 20
        "10000001001110000000000000000001",  -- Zeile 21
        "10000001001111000000000000000001",  -- Zeile 22
        "10000010000111000000000000000001",  -- Zeile 23
        "10000010000111100000000000000001",  -- Zeile 24
        "10000011111111100000000000000001",  -- Zeile 25
        "10000100000011110000000000000001",  -- Zeile 26
        "10000100000001110000000000000001",  -- Zeile 27
        "10011110000111111100000000000001",  -- Zeile 28
        "10000000000000000000000000000001",  -- Zeile 29
        "10000000000000000000000000000001",  -- Zeile 30
        "11111111111111111111111111111111" -- Zeile 31
    );

begin

    -- generation of a 25 MHz clock
    process(clk)
    begin
        if rising_edge(clk) then
            Takt25MHz <= not Takt25MHz;
        end if;
    end process;

    process(Takt25MHz)
        variable vsl_hCt, vsl_vCt : unsigned(9 downto 0);
        variable Zeilenwechsel : boolean;
        variable tmp : std_logic_vector(31 downto 0);
    begin
        if rising_edge(Takt25MHz) then
            -- pixel counter, line sync. and blank signal generation
            hCounter <= hCounter + 1;
            Zeilenwechsel := false;
            case hCounter is
                when 95 =>
                    hs <= '0';  -- line syncronization off
                when 143 =>
                    hBlack <= '0'; -- horizontal blank off
                when 783 =>
                    hBlack <= '1'; -- horizontal blank on
                when 799 =>
                    hCounter <= 0; -- next line
                    Zeilenwechsel := true;
                    hs <= '1';  -- line syncronization on
                when others =>
                    null;
            end case;
            
            -- line counter, image sync. and blank signal generation
            if Zeilenwechsel then
                vCounter <= vCounter + 1;
                case vCounter is
                    when 1 =>
                        vs <= '0';
                    when 30 =>
                        vBlack <= '0';
                    when 511 =>
                        vBlack <= '1';
                    when 520 =>
                        vCounter <= 0;
                        vs <= '1';
                    when others =>
                        null;
                end case;
            end if;
            
            -- generation of image elements
            -- convertion of pixel and line conter values to bit vectors
            vsl_hCt := to_unsigned(hCounter, 10);

            if hBlack = '1' or vBlack = '1' then
                rgb <= schwarz;
            else
                --  vertical linie (red)
                if hCounter = 222 then
                    rgb <= rot;
                -- horizontal linie (green)
                elsif vCounter = 178 then
                    rgb <= gruen;
                -- diagonal linie (blue)
                elsif vCounter = hCounter then
                    rgb <= blau;
                
                -- square
                elsif vsl_hCt(9 downto 6) = x"4" and vsl_vCt(9 downto 6) = x"3" then
                    rgb <= violett;
            
                -- grid
                elsif vsl_hCt(3 downto 0) = x"2" or vsl_vCt(3 downto 0) = x"2" then
                    rgb <= schwarz;

                -- display the image from the read only memory
                elsif vsl_hCt(9 downto 6) = x"5" and vsl_vCt(9 downto 6) = x"6" then
                    tmp := Bild(to_integer(vsl_vCt(5 downto 1)));
                    if tmp(to_integer(vsl_hCt(5 downto 1))) = '1' then
                        rgb <= gelb;
                    else
                        rgb <= cyan;
                    end if;
                
                -- background color
                else
                    rgb <= weis;
                end if;
            end if;
        end if;
    end process;

end architecture;