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-- a4_temp.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;


entity a4_pwm is
    port(
        clk : in std_logic;
        P10 : in std_logic;  -- temperatur sensor
        P12 : out std_logic; -- fan
        P16 : out std_logic; -- heating resistor
        sw : in std_logic_vector(3 downto 0);
        la : out std_logic_vector(0 downto 0);
        led_7seg : out std_logic_vector(7 downto 0);
        an_7seg : out std_logic_vector(3 downto 0)
    );
end entity;

architecture synth of a4_pwm is
    
begin

    -- fan switch
    P12 <= not sw(1);
    -- heiting switch
    P16 <= not sw(0);
    -- LA output to record the data from the temerature sensor
    la(0) <= P10;

end architecture;