--------------------------------------------------------------------------------
-- a3_rs232_tb.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity a3_rs232_tb is
end entity;

architecture sim of a3_rs232_tb is

    constant sim_time : time := 2 ms;
    constant clk_period : time := 650 ns;

    signal clk_16x_baud : std_logic := '0';
    signal txd, req, grant : std_logic := '0';
    signal data : std_logic_vector(7 downto 0) := x"00";
    
begin

    -- generate clock with a 16 times higer baude rate
    process
    begin
        while NOW < sim_time loop
            wait for clk_period / 2;
            clk_16x_baud <= '1';
            wait for clk_period / 2;
            clk_16x_baud <= '0';
        end loop;
        wait;
    end process;

    -- Instance of the transmitter
    sender_inst : entity work.a3_rs232_sender
        port map(
            clk_16x_baud => clk_16x_baud,
            txd          => txd,
            data         => data,
            req          => req,
            grant        => grant
        );

    process
    begin
        -- pause sending
        wait for 16 * clk_period;

        -- send 10 different characters
        for i in 0 to 9 loop
            data <= std_logic_vector(to_unsigned(i, 8) + x"30");

            -- activate request signal
            req <= '1';
            -- wait on acknowledge
            wait until rising_edge(clk_16x_baud) and grant = '1';
            -- deactivate request signal
            req <= '0';
            -- wait on acknowledge
            wait until rising_edge(clk_16x_baud) and grant = '0';

            -- pause after sending
            wait for 128 * clk_period;
        end loop;

        wait;
    end process;

end architecture;