//***********************************************************************************
//*	     File Name:	seven_seg.v
//*	       Version:	1.00
//*		  		 Date:	May 8, 2002
//*	File Hierarchy:	Low level module
//*	  Dependencies:	None
//*  
//*	      Designer:	Nasser Poureh
//*	       Company:	Insight Electronics
//*
//*
//*	   Discription:	This module tests the 7-Segment LED display.
//*
//* 			               
//************************************************************************************


module seven_seg (clk_100, resetn, seg_led_1, seg_led_2, user_led);

input				clk_100;
input				resetn;

output	[6:0]	seg_led_1;
output	[6:0]	seg_led_2;
output			user_led;


reg			[25:0]	led_count;
reg			[3:0] 	led_seg_count;
reg			[6:0]		seg_led_1;
reg			[6:0]		seg_led_2;
wire						led_count_en;



//	The following block encodes a binary number (0-9) to 7-segment LED display
//	outputs.

always @(led_seg_count)
	begin
			case (led_seg_count)
						0:	begin 
							seg_led_1	<= 7'b0111111;	
							seg_led_2	<= 7'b0111111; 
							end
						1:	begin 
							seg_led_1	<= 7'b0000110;	
							seg_led_2	<= 7'b0000110; 
							end	
						2:	begin 
							seg_led_1	<= 7'b1011011;	
							seg_led_2	<= 7'b1011011; 
							end
						3:	begin 
							seg_led_1	<= 7'b1001111;	
							seg_led_2	<= 7'b1001111; 
							end
						4:	begin 
							seg_led_1	<= 7'b1100110;	
							seg_led_2	<= 7'b1100110; 
							end
						5:	begin 
							seg_led_1	<= 7'b1101101;	
							seg_led_2	<= 7'b1101101; 
							end
						6:	begin 
							seg_led_1	<= 7'b1111101;	
							seg_led_2	<= 7'b1111101; 
							end
						7:	begin 
							seg_led_1	<= 7'b0000111;	
							seg_led_2	<= 7'b0000111; 
							end
						8:	begin 
							seg_led_1	<= 7'b1111111;	
							seg_led_2	<= 7'b1111111; 
							end
						9:	begin 
							seg_led_1	<= 7'b1101111;	
							seg_led_2	<= 7'b1101111; 
							end
				default:	begin 
							seg_led_1	<= 7'b0000000;	
							seg_led_2	<= 7'b0000000; 
							end
			endcase
	end


//	The following block generates numbers 0-9 to be displayed on the 7-segment
//	display. This 4-bit counter is loaded with the binary value of the on-board
//	DIP switch on reset. Once the reset goes inactive, the count will begin. The
//	counter will hold its last count when the count_hold_n signal goes active. This
//	4-bit counter will only count 0-9 and is reset to zero when the counter reaches
//	decimal 9.

always @(posedge clk_100)
	begin
		if (!resetn)
				led_seg_count <= 4'hf;
		else if ((led_seg_count == 4'h9) & (led_count_en == 1'b0))
				led_seg_count <= 0;
		else if (led_count_en == 1'b0)
				led_seg_count <= led_seg_count + 1;
	end





//	The following counter is used as a prescaler to the above 4-bit counter.
//	The input clock is divided by hex 3ffffff to enable the 4-bit counter.

always @(posedge clk_100)
	begin
		if (!resetn)
			led_count <= 0;
		else
			led_count <= led_count + 1;
	end

assign	led_count_en	= !(led_count == 26'h3ffffff);
assign	user_led			= seg_led_1[0];


endmodule